`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/10/27 14:42:03
// Design Name: 
// Module Name: Clock
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Clock(
    input clk,
    output reg clk_1ms,
    output reg clk_10ms,
    output reg clk_100ms,
    output reg clk_1s,
    output reg clk_1min
    );
    
    reg [31:0]q=0;
    reg [31:0]p=0;
    reg [31:0]r=0;
    reg [31:0]s=0;
    reg [31:0]t=0;
    
    
    always @(posedge clk)
    if(q==41666)
    begin
        q<=0;
        clk_1ms<=!clk_1ms;
    end
    else
        q<=q+1;
    
    always @(posedge clk_1ms)
    if(s==5)
    begin
        s<=0;
        clk_10ms<=!clk_10ms;
    end
    else
        s<=s+1;
        
  always @(posedge clk_10ms)
    if(p==5)
    begin
        p<=0;
        clk_100ms<=!clk_100ms;
    end
    else
        p<=p+1;
        
    always @(posedge clk_100ms)
    if(r==5)
    begin
        r<=0;
        clk_1s<=!clk_1s;
    end
    else
        r<=r+1;
        
    always @(posedge clk_1s)
    if(t==30)
    begin
        t<=0;
        clk_1min<=!clk_1min;
    end
    else
        t<=t+1;
           

    

    

      
  
    
  endmodule
